题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);

wire	[7:0]	d0,d1,d2;

min_num	u0
(
.clk (clk) ,
.rst_n (rst_n),
.a(a),
.b(b),

.c(d0)
);

min_num	u1
(
.clk (clk) ,
.rst_n (rst_n),
.a(b),
.b(c),

.c(d1)
);

min_num	u2
(
.clk (clk) ,
.rst_n (rst_n),
.a(d0),
.b(d1),

.c(d2)
);

assign	d = d2;

endmodule



module	min_num
(
input	clk	  ,
input	rst_n ,
input [7:0]  a,
input [7:0]  b,

output reg [7:0] c
);

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		c	<=	8'd0;
	else	if(a<b)
		c	<=	a;
	else
		c	<=	b;

endmodule