题解 | #不重叠序列检测#

此题只需要使用2个4bit的位作为状态标识即可，实际上只需12个状态，话不多说，直接上代码与仿真。

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

reg [3:0] state,next_state;
	
always@(*)begin
	case(state)
		0:		next_state = !data ? 1 : 7 ;
		1:		next_state =  data ? 2 : 8 ;
		2:		next_state =  data ? 3 : 9 ;
		3:		next_state =  data ? 4 : 10;
		4:		next_state = !data ? 5 : 11;
		5:		next_state = !data ? 6 : 12;
		6:		next_state = !data ? 1 : 7 ;
        12:     next_state = !data ? 1 : 7 ;
		default:next_state = state + 1;
	endcase
end

always@(posedge clk,negedge rst_n)begin
	if(!rst_n)begin
		state <= 0;
	end
	else begin
		state <= next_state;
	end
end

always@(*)begin
	match = (state==6);
	not_match = (state==12);
end

endmodule

`timescale  1ns / 1ps
module tb_sequence_detect;

// sequence_detect Parameters
parameter PERIOD  = 10;


// sequence_detect Inputs
reg   clk                                  = 0 ;
reg   rst_n                                = 0 ;
reg   data                                 = 0 ;

// sequence_detect Outputs
wire  match                                ;
wire  not_match                            ;


initial
begin
    $dumpfile ("HDL_bit_wave.vcd");
    $dumpvars;
    forever #(PERIOD/2)  clk=~clk;
end

initial
begin
    #(PERIOD*2) rst_n  =  1;
end

sequence_detect  u_sequence_detect (
    .clk                     ( clk         ),
    .rst_n                   ( rst_n       ),
    .data                    ( data        ),

    .match                   ( match       ),
    .not_match               ( not_match   )
);

initial
begin
    #(PERIOD);
    #(PERIOD) data   =  0;
    #(PERIOD) data   =  1;
    #(PERIOD) data   =  1;
    #(PERIOD) data   =  1;
    #(PERIOD) data   =  0;
    #(PERIOD) data   =  0;

    #(PERIOD) data   =  0;
    #(PERIOD) data   =  0;
    #(PERIOD) data   =  1;
    #(PERIOD) data   =  1;
    #(PERIOD) data   =  1;
    #(PERIOD) data   =  0;

    #(PERIOD*4);
    $finish;
end

endmodule