题解 | #全加器#

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);

wire    S0,C0;
wire    S1,C1;

add_half    u0
(
   .A (A),
   .B (B),
 
   .S (S0),
   .C (C0)  
);

add_half    u1
(
   .A (S0),
   .B (Ci),
 
   .S (S1),
   .C (C1)  
);

assign  S   =   S1;
assign  Co  =   C0 | C1;




endmodule