题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
//状态变量
	reg[3:0] pstate,nstate;
	parameter idle=4'd0,
			  s1_d0=4'd1,
			  s2_d01=4'd2,
			  s3_d011=4'd3,
			  s4_d0110=4'd4;
//状态更新，时序逻辑
always @(posedge clk or negedge rst_n)begin
	if(!rst_n)
		pstate <= idle;
	else
		pstate <= nstate;
end
//状态转移条件，组合逻辑
always@(*)begin
	case(pstate)
		idle:begin
			if(data_valid&&!data)
				nstate=s1_d0;
			else
				nstate=idle;
		end
		s1_d0:begin
			if(data_valid&&data)
				nstate = s2_d01;
			else if(data_valid&&!data)
				nstate = s1_d0;
			else
				nstate = s1_d0;	
		end
		s2_d01:begin
			if(data_valid&&data)
				nstate = s3_d011;
			else if(data_valid&&!data)
				nstate = s1_d0;
			else
				nstate = s2_d01;
		end
		s3_d011:begin
			if(data_valid&&!data)
				nstate = s4_d0110;
			else if(data_valid&&data)
				nstate =idle;
			else 
				nstate = s3_d011;
		end
		s4_d0110:begin
			if(data_valid&&data)
				nstate = idle;
			if(data_valid&&!data)
				nstate = s1_d0;
			else
				nstate = idle;
		end
		default:
			nstate=idle;
		
	endcase
end 
//输出，组合逻辑
always@(pstate or rst_n)
begin
	if(!rst_n)
		match = 1'b0;
	else if(pstate==s4_d0110)
		match=1'b1;
	else
		match=1'b0;
end

endmodule

序列检测还是更喜欢用缓存序列对比法，但是状态机法也是一定要会的