题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);

// clk_a domain
reg [3:0] data_in_reg;
always@(posedge clk_a or negedge arstn)begin
	if(!arstn)
		data_in_reg <= 4'd0;
	else
		data_in_reg <= data_in;
end

reg data_en_reg;
always@(posedge clk_a or negedge arstn)begin
	if(!arstn)
		data_en_reg <= 1'b0;
	else
		data_en_reg <= data_en;
end

// clk_a domain to clk_b domain
reg [1:0] data_en_sync;
always@(posedge clk_b or negedge brstn)begin
	if(!brstn)
		data_en_sync <= 2'd0;
	else
		data_en_sync <= {data_en_sync[0],data_en_reg};
end

// clk_b domain
always@(posedge clk_b or negedge brstn)begin
	if(!brstn)
		dataout <= 4'd0;
	else
		dataout <= data_en_sync[1] ? data_in_reg : dataout;
end

endmodule