题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);

reg [3:0] cnt ;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		cnt <= 'd0;
	else if (cnt == 'd9 && mode == 'd1)
		cnt <= 'd0 ;
	else if (cnt == 'd0 && mode == 'd0)
		cnt <= 'd9 ;
	else if(mode)
		cnt <= cnt + 'd1 ;
	else 
		cnt <= cnt - 'd1 ;
end

always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		zero <= 'd0;

	else if(cnt == 'd0)
		zero <= 'd1 ;
	else
		zero <= 'd0 ;
end

always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		number <= 'd0;
	else 
		number <= cnt ;
end




endmodule