题解 | #简易秒表#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
	
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		second <= 'd0;
		minute <= 'd0 ;
	end
	else if (second == 'd60) begin
		second <= 'd1 ;
		minute <= minute + 1 ;
	end
	else if(minute == 'd60)
		second <= 0 ;
	else 
		second <= second + 'd1 ;
end
	
endmodule