题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//

parameter S0 = 5'b00001 ;
parameter S1 = 5'b10000 ;
parameter S2 = 5'b01000 ;
parameter S3 = 5'b00100 ;
parameter S4 = 5'b00010 ;

reg [4:0] Cur_state ;
reg [4:0] Nxt_state ;

//第一段式
always@(posedge clk or negedge rst)  begin
	if(!rst)
		Cur_state <= S0 ;
	else
		Cur_state <= Nxt_state ;
end

//第二段式
always@(*) begin
	if(!rst) begin
		flag = 0;
		Nxt_state = S0 ;
	end
	else	
		case(Cur_state)
		S0:if(data == 0) begin
			flag = 0;
			Nxt_state = S0 ;
		end 
		else begin
			flag = 0;
			Nxt_state = S1 ;
		end

		S1:if(data == 0) begin
			flag = 0;
			Nxt_state = S1 ;
		end 
		else begin
			flag = 0;
			Nxt_state = S2 ;
		end

		S2:if(data == 0) begin
			flag = 0;
			Nxt_state = S2 ;
		end 
		else begin
			flag = 0;
			Nxt_state = S3 ;
		end

		S3:if(data == 0) begin
			flag = 0;
			Nxt_state = S3 ;
		end 
		else begin
			flag = 0;
			Nxt_state = S4 ;
		end

		S4:if(data == 0) begin
			flag = 1;
			Nxt_state = S0 ;
		end 
		else begin
			flag = 1;
			Nxt_state = S1 ;
		end

		endcase

end


//*************code***********//
endmodule