题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,   //输入数据有效信号
	input	 			ready_b		,   //下游是否准备好接收
 
 	output		 		ready_a		,   //是否准备接收上游数据
 	output	reg			valid_b		,   //输出有效信号
	output  reg [9:0] 	data_out
);

reg [1:0]cnt; //接收4个数据计数器

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    cnt <= 2'b0;
	else if (cnt == 2'd3 && ready_a == 1'b1 && valid_a == 1'b1)    //在输入数据有效，而且准备好接收上游信号，而且接收导里4个数据
	    cnt <= 2'b0;
	else if (valid_a == 1'b1 && ready_a == 1'b1)                   //在输入数据有效，而且准备好接收上游信号
	    cnt <= cnt + 1'b1;
	else 
	    cnt <= cnt;

//输出有效信号赋值
always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    valid_b <= 1'b0;
	else if (cnt == 2'd3 && valid_a == 1'b1)
	    valid_b <= 1'b1;
	else if (ready_a == 1'b1 && ready_b == 1'b1 && valid_a == 1'b1)
	    valid_b <= 1'b0;
	else 
	    valid_b <= valid_b;

//输出赋值
always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    data_out <= 10'b0;
	else if (cnt == 2'b0 && ready_a == 1'b1 && valid_a == 1'b1)     //在计数器接收到第一个数据后，直接输出
	    data_out <= data_in;
	else if (ready_a == 1'b1 && valid_a == 1'b1)                    //在计数器接收到第二个，第三个，第四个数据后是累加输出
	    data_out <= data_in + data_out;
	else 
	    data_out <= data_out;

//
assign ready_a = (valid_b == 1'b1 && ready_b == 1'b0) ? 1'b0 : 1'b1;




endmodule