题解 | #脉冲同步电路#

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
reg			data_reg;
always @(posedge clk_fast or negedge rst_n) begin
	if(!rst_n) begin
		data_reg <= 1'b0 ;
	end
	else if(data_in)begin
		data_reg <= ~data_reg ;
	end
end
reg			data_t1 ,data_t2 ;
always @(posedge clk_slow or negedge rst_n) begin
	if(!rst_n) begin
		data_t1 <= 1'b0 ;
		data_t2 <= 1'b0 ;
	end
	else begin
		data_t1 <= data_reg ;
		data_t2 <= data_t1 ;	
	end
end
reg			data_tmp ;
always @(posedge clk_slow or negedge rst_n) begin
	if(!rst_n) begin
		data_tmp <= 1'b0 ;
	end
	else begin
		data_tmp <= data_t2 ;
	end
end
assign dataout = data_t2 ^ data_tmp ;
endmodule