题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
reg		[8:0]	a_9b ;
 always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		a_9b <= 9'b0 ; 
	end
	else begin
		a_9b <= {a_9b[7:0],a};
	end
 end 

 always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		match <= 1'b0 ;
	end
	else if(a_9b[2:0] == 3'b110 && a_9b[8:6]== 3'b011) begin
		match <= 1'b1 ;
	end
	else begin
		match <= 1'b0 ;
	end
 end
endmodule