题解 #使用8线-3线优先编码器实现16线-4线优先编码器

`timescale 1ns/1ns
module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,  
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);
assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];
assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);       
endmodule
module encoder_164(
   input      [15:0]      A   ,
   input                  EI  , 
   output wire [3:0]      L   ,
   output wire            GS  ,
   output wire            EO    
);
wire        GS1,EO1 ,GS2;
wire        [2:0]   Y1 ,Y2;
    encoder_83 U_ENCODER_83_U0 
    (
   /*input      [7:0] */      .I (A[15:8])  ,
   /*input            */      .EI(EI)  ,
   
   /*output wire [2:0]*/      .Y (Y1)  ,
   /*output wire      */      .GS(GS1) ,
   /* wire            */      .EO(EO1)   
    );
    encoder_83 U_ENCODER_83_U2 
    (
   /*input      [7:0] */      .I (A[7:0])  ,
   /*input            */      .EI(EO1)  ,
   
   /*output wire [2:0]*/      .Y (Y2)  ,
   /*output wire      */      .GS(GS2) ,
   /* wire            */      .EO(EO)   

    );
    assign  GS = GS1 | GS2 ;
    assign  L[3] = GS1 ;
    assign  L[2] = Y1[2] | Y2[2] ;
    assign  L[1] = Y1[1] | Y2[1] ;
    assign  L[0] = Y1[0] | Y2[0] ;
endmodule