题解 | #多功能数据处理器#

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
	input signed[7:0]a,
	input signed[7:0]b,
	input [1:0]select,
	output reg signed [8:0]c
);
always @ (posedge clk or negedge rst_n)
 if (!rst_n)
    c<=9'b0;
else begin 
    case(select)
    2'd0: c<={a[7],a};
    2'd1: c<={b[7],b};
	2'd2: c<={a[7]+b[7],a+b};
    2'd3: c<={a[7]-b[7],a-b};
	default: c<=9'b0;
	endcase
end


endmodule