题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

	reg [2:0]cnt;
	reg [5:0]b_temp;
	always@(posedge clk or negedge rst_n)//计数
	if (!rst_n)
		begin
			cnt<=3'b0;
			ready_a<=0;
		end
	else if(valid_a)
		begin
			cnt<=(cnt==3'b101)?3'b000:cnt+1'b1;
			ready_a<=1'b1;
		end
	else
		begin
			cnt<=cnt;
			ready_a<=1'b1;
		end

	always@(posedge clk or negedge rst_n)//输入拼接
	if (!rst_n)
		begin
			b_temp<=6'b000_000;
		end
	else if(valid_a)
		begin
			b_temp<={data_a, b_temp[5:1]};
		end
	else
		begin
			b_temp<=b_temp;
		end

	always@(posedge clk or negedge rst_n)//输出
	if (!rst_n)
		begin
			data_b<=6'b000_000;
			valid_b<=1'b0;
		end
	else if(cnt==5'b101)
		begin
			valid_b<=1'b1;
			data_b<={data_a, b_temp[5:1]};//cnt=6时还需要把data值加入data_b，在下一个周期输出
		end
	else
		begin
			valid_b<=0;
			data_b<=data_b;
		end


endmodule