题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	output[7:0]d
);
wire [7:0]d1,d2;
min min1(clk,rst_n,a,b,d1);
min min2(clk,rst_n,a,c,d2);
min min3(clk,rst_n,d1,d2,d);
endmodule

module min(
input clk,
input rst,
input [7:0]a,
input [7:0]b,
output reg [7:0] out
);
always@(posedge clk or negedge rst)
begin
if(rst)
begin
if(a<b) out<=a;
else out<=b;
end
else out<=0;
end
endmodule