题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
reg [3:0] r_number;

always@(*) begin
	if(rst_n==1'b0) zero = 0;
	else if(number==0) zero = 1;
	else zero = 0;
end

always@(posedge clk,negedge rst_n) begin
	if(rst_n==1'b0) r_number <= 0;
	else if(set==1) r_number <= set_num;
	else r_number <= r_number +1;
end

always@(posedge clk,negedge rst_n) begin //延后一拍
	if(rst_n==1'b0) number <= 0;
	else number <= r_number;
end

endmodule