题解 | #简易秒表#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);

reg [5:0] scnt,mcnt;

always@(posedge clk, negedge rst_n) begin
	if(rst_n==1'b0) second <= 0;
	else if(second == 60) second <= 1;
	else if(minute == 60) second <= 0;
	else second <= second + 1;
end

always@(posedge clk, negedge rst_n) begin
	if(rst_n==1'b0) minute <= 0;
	else if(minute == 60) minute<= 0;
	else if(second == 60) minute <= minute + 1;
end
	
endmodule