题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//

//分三段式来写，理解起来会更加简单明了//

//由于运算周期为4，因此建立一个周期为四的计数器//
reg [2:0] counter;
always @ (posedge clk or negedge rst) begin
    if(~rst)
        counter<=0;
    else if (counter==3'd4)
        counter<=1;
    else
    counter<=counter+1;
end

//因为输入信号d不是随时有效的，只在第一个周期前有效，因此建立一个锁存器保存输入信号的值//
reg [7:0] d_temp;
always @ (*) begin
    if (counter==3'd0 | counter==3'd4)
    d_temp<=d;
    else
    d_temp<=d_temp;
end

//根据计数器的值来执行对应的乘法运算//
always @ (posedge clk or negedge rst) begin
    if (~rst) begin
        out<=0;
        input_grant<=0;
    end
    else begin
           case(counter)
             3'd0: begin out<=d_temp; input_grant<=1;end
             3'd1: begin out<={1'b0,d_temp,2'b0}-d_temp;input_grant<=0;end
             3'd2: begin out<={d_temp,3'd0}-d_temp;input_grant<=0;end
             3'd3: begin out<={d_temp,3'd0};input_grant<=0;end
             3'd4: begin out<=d_temp; input_grant<=1;end
           endcase
    end
end

//*************code***********//
endmodule