题解 | #实现3-8译码器①#

`timescale 1ns/1ns

module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output wire       Y0_n   ,  
   output wire       Y1_n   , 
   output wire       Y2_n   , 
   output wire       Y3_n   , 
   output wire       Y4_n   , 
   output wire       Y5_n   , 
   output wire       Y6_n   , 
   output wire       Y7_n   
);


//单独38译码器真值表
// |    A2  |   A1  |   A0  |   |   Y0_n    Y1_n    Y2_n    Y3_n    Y4_n    Y5_n    Y6_n    Y7_n
// |    0   |   0   |   0   |   |    0       1       1       1       1       1       1       1
// |    0   |   0   |   1   |   |    1       0       1       1       1       1       1       1
// |    0   |   1   |   0   |   |    1       1       0       1       1       1       1       1
// |    0   |   1   |   1   |   |    1       1       1       0       1       1       1       1
// |    1   |   0   |   0   |   |    1       1       1       1       0       1       1       1
// |    1   |   0   |   1   |   |    1       1       1       1       1       0       1       1
// |    1   |   1   |   0   |   |    1       1       1       1       1       1       0       1
// |    1   |   1   |   1   |   |    1       1       1       1       1       1       1       0


//Y0_n=A0|A1|A2
//Y1_n=~A0|A1|A2
//Y2_n=A0|(~A1)|A2
//Y3_n=(~A0)|(~A1)|A2
//Y4_n=A0|A1|(~A2)
//Y5_n=(~A0)|A1|(~A2)
//Y6_n=A0|(~A1)|(~A2)
//Y7_n=(~A0)|~A1|~A2

wire OENA=E1_n|E2_n|E3==0;
assign Y0_n=A0|A1|A2|OENA;
assign Y1_n=~A0|A1|A2|OENA;
assign Y2_n=A0|(~A1)|A2|OENA;
assign Y3_n=(~A0)|(~A1)|A2|OENA;
assign Y4_n=A0|A1|(~A2)|OENA;
assign Y5_n=(~A0)|A1|(~A2)|OENA;
assign Y6_n=A0|(~A1)|(~A2)|OENA;
assign Y7_n=(~A0)|~A1|~A2|OENA;


















endmodule