题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);

//状态定义
parameter S0 = 2'd0;
parameter S1 = 2'd1;
parameter S2 = 2'd2;
parameter S3 = 2'd3;

//状态寄存器定义
reg [1:0]curr_state;
reg [1:0]next_state;


//状态输出寄存器
reg Y_reg;
//组合逻辑描述状态转移条件
always@(*)begin
    case(curr_state)
        S0: next_state <= A? S3:S1;
        S1: next_state <= A? S0:S2;
        S2: next_state <= A? S1:S3;
        S3: next_state <= A? S2:S0;
        default: next_state <= S0;
    endcase
end

//时序逻辑实现状态转移
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        curr_state <= S0;
    else
        curr_state <= next_state;
end 

//组合逻辑描述输出
always@(*)begin
    if(!rst_n)
        Y_reg <= 0;
    else if(curr_state == S3)
        Y_reg <= 1;
    else    
        Y_reg <= 0;
end

assign Y = Y_reg;
endmodule