题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//
localparam WIDTH = 4,
            DEPTH = 128;
integer i;
reg [WIDTH-1:0] ram_memory [DEPTH-1:0];
always@(posedge clk or negedge rst) begin
    if(~rst) 
        for(i=0;i<128;i=i+1) ram_memory[i] <= 0;
    else if (enb) 
        ram_memory[addr] <= w_data;
end
assign r_data = (enb)? 0 : ram_memory[addr];
//*************code***********//
endmodule