题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
//状态定义
parameter S0 = 2'd0;
parameter S1 = 2'd1;
parameter S2 = 2'd2;
parameter S3 = 2'd3;


//状态寄存器
reg [1:0]curr_state;
reg [1:0]next_state;

//组合逻辑判断状态转移条件
always@(*)begin
	case(curr_state)
		S0: next_state <= data? S1:S0;
		S1: next_state <= data? S2:S1;
		S2: next_state <= data? S3:S2;
		S3: next_state <= data? S0:S3;
		default: next_state <= S0;
	endcase
end

//时序逻辑实现状态转移
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		curr_state <= S0;
		//flag <= 1'b0;
	end
	else
		curr_state <= next_state; 
end

//时序逻辑实现状态机输出
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		flag <= 1'b0;
	end
	else if(curr_state == S3 &&next_state == S0)
		flag <= 1'b1;
	else	
		flag <= 1'b0;
end

//*************code***********//
endmodule