题解 | #异步复位同步释放#

`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );

//*************code***********//

    reg rst_n1,rst_n2;

    always @(posedge clk or negedge rst_n) begin
        if(rst_n == 1'b0)begin
            rst_n1 <= 1'b0;
            rst_n2 <= 1'b0;
        end
        else begin
            rst_n1 <= 1'b1;
            rst_n2 <= rst_n1;
        end
    end

    always @(posedge clk or negedge rst_n2) begin
        if(rst_n2 == 1'b0)
            dout <= 1'b0;
        else
            dout <= d;
    end

//*************code***********//
endmodule