题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

	parameter SEQ = 8'b01110001;

	reg [7:0] data_temp;

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_temp <= 8'd0;
		else
			data_temp <= {data_temp[6:0],a};
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n ==  1'b0)
			match <= 1'b0;
		else if(data_temp == SEQ)
			match <= 1'b1;
		else
			match <= 1'b0;
	end
endmodule