题解 | #根据状态转移图实现时序电路#
根据状态转移图实现时序电路
https://www.nowcoder.com/practice/e405fe8975e844c3ab843d72f168f9f4
`timescale 1ns/1ns
module seq_circuit(
input C ,
input clk ,
input rst_n,
output Y //为了写三段式更清楚，我将Y改为reg型；
//如果用wire型的话，第三段改用assign赋值即可；
);
reg [1:0] current_state;
reg [1:0] next_state;
reg Y;
parameter s0=2'b00,
s1=2'b01,
s2=2'b10,
s3=2'b11;
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
current_state <= s0;
else
current_state <= next_state;
end
always@(*) begin
case(current_state)
s0:
next_state=(C)?s1:s0;
s1:
next_state=(C)?s1:s3;
s2:
next_state=(C)?s2:s0;
s3:
next_state=(C)?s2:s3;
default:
next_state <= s0;
endcase
end
always@(*) begin
if(!rst_n)
Y <= 1'b0;
else if((current_state==s3)||((current_state==s2)&&(C==1)))
Y <= 1'b1;
else
Y <= 1'b0;
end
endmodule
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