题解 | #状态机与时钟分频-新状态机写法#

状态机与时钟分频

https://www.nowcoder.com/practice/25d694a351b748d9808065beb6120025

1、不需要next_state,参考达尔闻的状态机写法。第一段写状态机的状态变化，第二段写输出状态

2、state == s0，因为是时序电路了，所以和组合逻辑的判断时机不一样。

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
    parameter [1:0] s0 = 2'b00, 
                    s1 = 2'b01,
                    s2 = 2'b10,
                    s3 = 2'b11;
    
    reg [1:0] state, next_state;
    
    always @ (posedge clk, negedge rst) begin
        if(!rst) 
            state <= s0;
        else begin
            case(state)
                s0: begin
                    state <= s1;
                end
                s1: begin
                    state <= s2;
                end  
                s2: begin
                    state <= s3;
                end                
                s3: begin
                    state <= s0;
                end
                default: begin
                    state <= s0;
                end
            endcase
        end
    end
    
    always @ (posedge clk, negedge rst) begin
        if(!rst) 
            clk_out <= 0;
        else if(state == s0) begin
            clk_out <= 1;
        end
        else begin
            clk_out <= 0;
        end
    end
    
//     always @ (posedge clk, negedge rst) begin
//         if(!rst) 
//             state <= s0;
//         else
//             state <= next_state;
//     end
    
//     always @ (state) begin
//         case(state)
//             s0: begin
//                 next_state <= s1;
//                 clk_out <= 1'b0;
//             end
//             s1: begin
//                 next_state <= s2;
//                 clk_out <= 1'b1;
//             end  
//             s2: begin
//                 next_state <= s3;
//                 clk_out <= 1'b0;
//             end   
//             s3: begin
//                 next_state <= s0;
//                 clk_out <= 1'b0;
//             end
//             default: begin
//                 next_state <= s0;
//                 clk_out <= 1'b0;
//             end
//         endcase
//     end
    
    


//*************code***********//
endmodule