面试系列:【4】timing_path&path_group
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关于path and path group
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本文针对常见的path和pathgroup 问题,做深入的分析和总结
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path 和path group 属于时序设计中的基本问题,属于必须掌握的知识点
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希望对大家的面试和工作有帮助
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Design and library objects
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Ports Versus Pins
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‘Ports’ are the inputs and outputs of the current design
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‘Pins’ are the inputs and outputs of any cell that isinstantiated in the current design
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PathDelay
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Path Delays are Based on Cell + Net Delays
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PathDelay
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Path delay section
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PathDelay
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Define setup timing constraints for all paths within a sequential design
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All input logic paths (startingat input ports)
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The internal (register to register) paths
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All output paths (ending at output ports)
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Starting at input ports and ending at output ports
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Static timing analysis Fundamentals
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Static Timing Analysis can determine if a circuit meetstiming constraints without dynamic simulation
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This involves three main steps:
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design is broken down into timingpaths
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The delay of each path is calculated
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All path delays are checked against timing constraints
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Static timing analysis Fundamentals
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Grouping of Timing Paths into Path Groups
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report_path_group
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Paths are grouped by the clocks controlling their endpoints
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Static timing analysis Fundamentals
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Timing Paths and Group Paths
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How many timing paths are there?
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How many path groups are there?
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Path and path group总结
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Path and path group 属于时序中的基础问题
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Path group 要尽量做到最简化
- 一定要学会画波形图和时序图,正确区分path和pathgroup,做到全覆盖
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