题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
    //FSM three segments
    //one-hot code
    parameter IDLE = 9'b0_0000_0001;
    parameter S0   = 9'b0_0000_0010;
    parameter S1   = 9'b0_0000_0100;
    parameter S2   = 9'b0_0000_1000;
    parameter S3   = 9'b0_0001_0000;
    parameter S4   = 9'b0_0010_0000;
    parameter S5   = 9'b0_0100_0000;
    parameter S6   = 9'b0_1000_0000;
    parameter S7   = 9'b1_0000_0000;
    
    //segment1:state coding,generate next state
    reg [8:0] cur_state, next_state;
    always@(*)begin
        case(cur_state)
            IDLE: next_state=(a==1'b0)? S0:IDLE;
            S0:   next_state=(a==1'b1)? S1:S0;
            S1:   next_state=(a==1'b1)? S2:IDLE;//前一个是0，不满足返回S0就行，前一个如果是1.不满足应该返回IDLE
            S2:   next_state=(a==1'b1)? S3:IDLE;
            S3:   next_state=(a==1'b0)? S4:IDLE;
            S4:   next_state=(a==1'b0)? S5:S0;
            S5:   next_state=(a==1'b0)? S6:S0;
            S6:   next_state=(a==1'b1)? S7:S0;
            S7:   next_state=IDLE;//(a==1'b1)? IDLE:IDLE;因为前一个状态是1
            default: next_state=IDLE;    
        endcase
    end
    //segment2:state transfer, generate current state;
    always@(posedge clk&nbs***bsp;negedge rst_n)begin
        if (!rst_n)
            cur_state<=IDLE;
        else
            cur_state<=next_state;            
    end
    //segment3:output register, generate outputdata;
    
    //assign match=(cur_state==S7);  //match is wire
    wire match_wire;
    assign match_wire=(cur_state==S7);
    always@(posedge clk&nbs***bsp;negedge rst_n)begin 
        if(!rst_n) 
            match<=1'b0;
        else
            match<=match_wire;
    end
  
endmodule