题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
//保证移位的乘法是基于第一个时钟周期，加一个寄存器，对输入寄存
//input_grant在每次第一次相乘时，被赋值1    
    //写在一个always里
   reg [1:0] count;//状态机计数；FSM
    reg [10:0] d_reg;
    always@(posedge clk&nbs***bsp;negedge rst)
        if(!rst) begin
            count<=2'b0;
            input_grant<=1'b0;
            out<=1'b0;
            d_reg<=11'b0;
        end
        else begin
            count<=count+1'b1;
            case(count)
                2'b00:begin
                    d_reg<=d;
                    input_grant<=1'b1;
                    out<=d;
                end
                2'b01:begin
                    input_grant<=1'b0;
                    out<=(d_reg<<2)-d_reg;
                end
                2'b10:begin
                    input_grant<=1'b0;
                    out<=(d_reg<<3)-d_reg;
                end
                2'b11:begin
                    input_grant<=1'b0;
                    out<=d_reg<<3;
                end    
                default : begin
                    out <= d;
                    input_grant <= 1'b0;
                end   
            endcase
        end
    //写在两个always块中
  /*      reg [1:0] count;    // 0 1 2 3
       always @ (posedge clk&nbs***bsp;negedge rst)
        begin
            if(~rst) begin
                count <= 2'b0;
            end
            else begin
                count <= count + 1'b1;
            end
        end

    // FSM
    reg [10:0] d_reg;
        always @ (posedge clk&nbs***bsp;negedge rst)
        begin
            if(~rst) begin
                out <= 11'b0;
                input_grant <= 1'b0;
                d_reg <= 11'b0;
            end
            else begin
                case( count )
                    2'b00 : begin
                        out <= d;
                        d_reg <= d;
                        input_grant <= 1'b1;
                    end
                    2'b01 : begin
                        //out <= d_reg + {d_reg, 1'b0};    // *1 + *2
                        out <= (d_reg<<2)-d_reg;    // *1 + *2
                        input_grant <= 1'b0;
                    end
                    2'b10 : begin
                        //out <= d_reg + {d_reg, 1'b0} + {d_reg, 2'b0};
                        out <= (d_reg<<3)-d_reg;    // *1 + *2
                        input_grant <= 1'b0;
                    end
                    2'b11 : begin
                        //out <= {d_reg, 3'b0};
                        out <= d_reg<<3;
                        input_grant <= 1'b0;
                    end
                    default : begin
                        out <= d;
                        input_grant <= 1'b0;
                    end
                endcase
            end
        end */

//*************code***********//
endmodule