题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);
    wire [4:0] g_buff ;
    wire [4:0] p_buff ;
    wire [4:0] c_buff ;
    wire [15:0] buff  ;
    wire [4:0] s_buff;
    assign S = s_buff[3:0] ;
    assign CO = c_buff[4] ;
    genvar i ;
    generate
        for(i=0;i<4;i=i+1) begin: buff_cal
            and(g_buff[i],A_in[i],B_in[i]);
            xor(p_buff[i],A_in[i],B_in[i]);
        end
    endgenerate
    assign c_buff[0] = C_1 ;
    generate
        for(i=1;i<5;i=i+1) begin: res_cal
            and(buff[i],p_buff[i-1],c_buff[i-1]);
            or (c_buff[i],g_buff[i-1],buff[i]);
            xor(s_buff[i-1],p_buff[i-1],c_buff[i-1]);
        end
    endgenerate
    
    
endmodule