题解 | #状态机与时钟分频#

因为是1/4分频，1/4占空比，所以直接在某一个周期亮起就ok了

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
    parameter [1:0] s0 = 2'b00, 
                    s1 = 2'b01,
                    s2 = 2'b10,
                    s3 = 2'b11;
    
    reg [1:0] state, next_state;
    
    always @ (posedge clk, negedge rst) begin
        if(!rst) 
            state <= s0;
        else
            state <= next_state;
    end
    
    always @ (state) begin
        case(state)
            s0: begin
                next_state <= s1;
                clk_out <= 1'b0;
            end
            s1: begin
                next_state <= s2;
                clk_out <= 1'b1;
            end  
            s2: begin
                next_state <= s3;
                clk_out <= 1'b0;
            end   
            s3: begin
                next_state <= s0;
                clk_out <= 1'b0;
            end
            default: begin
                next_state <= s0;
                clk_out <= 1'b0;
            end
        endcase
    end
    
    


//*************code***********//
endmodule