题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p( input clk ,
input rst_n , input valid_a , input data_a ,

output	reg 		ready_a		,
output	reg			valid_b		,
output  reg [5:0] 	data_b

); always @(posedge clk or negedge rst_n)begin if(!rst_n)begin ready_a<=1'd0;end else begin ready_a<=1'd1;end end

reg [3:0] cnt;
reg [5:0] data_out;
reg isDone;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt<=4'd0;
        data_b<=6'd0;
        valid_b<=1'd0;
        data_out<=6'd0;
    end else if(valid_a & ready_a)begin
        case(cnt)
            4'd0:begin
                data_out<={data_a,5'b0000};
                valid_b<=1'b0;
                cnt<=cnt+1'b1;
            end
            4'd1,4'd2,4'd3,4'd4:begin
                data_out<={data_a,data_out[5:1]};
                cnt<=cnt+1'd1;
            end
            4'd5:begin
                cnt<=4'd0;
                data_b<={data_a,data_out[5:1]};
                valid_b<=1'b1;
            end
        endcase
    end
        
    
    
    
end

endmodule