题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match );

reg [3:0]state, next_state
reg match_pre;
localparam IDLE=8, S0=0, S01=1, S011=2, S0111=3, S01110=4, S011100=5, S0111000=6, S01110001=7;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n) state <= IDLE;
    else state <= next_state;
end
always@(*)begin
    case(state)
      IDLE:next_state = a? IDLE:S0;
      S0:  next_state = a? S01:S0;
      S01: next_state = a? S011:S0;
      S011:next_state = a? S0111:S0;
      S0111:next_state = a? IDLE:S01110;
      S01110:next_state = a? S01:S011100;
      S011100:next_state = a? S01:S0111000;
      S0111000:next_state = a? S01110001:S0;
      S01110001:next_state = a? S011:S0;
    endcase
end
    always@(posedge clk or rst_n)begin
    if(!rst_n) match <= 0;
    else if(state==S01110001) match <= 1;
    else match <= 0;
end

/* always@(posedge clk or rst_n)begin
        if(!rst_n) match_pre <= 0;
        else if(next_state==S01110001) match_pre <= 1;
        else match_pre <= 0;
    end
     always@(posedge clk or negedge rst_n)begin
        if(!rst_n) match <= 0;
        else if(match_pre) match <= 1;
        else match <= 0;
    end*/
endmodule

用状态机拉了， 比如我