题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
    
    parameter a = 3'b000, b=3'b001, c=3'b010, d=3'b011, e=3'b100, f=3'b101, idle=3'b111;
    reg [2:0] sta, nsta;
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            sta <= idle;
        end else begin
            sta <= nsta;
        end
    end
    
    always @(*) begin
        {data,nsta} = {1'b0,idle};
        case (sta)
            idle : {data,nsta} = {1'b0,a};
            a : {data,nsta} = {1'b0,b};
            b : {data,nsta} = {1'b0,c};
            c : {data,nsta} = {1'b1,d};
            d : {data,nsta} = {1'b0,e};
            e : {data,nsta} = {1'b1,f};
            f : {data,nsta} = {1'b1,a};
        endcase
    end

endmodule